1. Technical Field of the Invention
The present invention relates to circuits and more particularly, to a single ended domino compatible dual function generator circuit.
2. Background Art
Domino circuits often require true and complementary data inputs signals to implement Boolean logic functions. While an inversion of the previous domino stage's output may suffice logically, it leads to functional race conditions. Specifically, a domino gate typically requires both its true and complementary inputs to have the same state (e.g., a logic low state) during the precharge phase. This requirement is violated if a simple inverter is placed at the output of the domino stage. To solve this problem, a fully dual-rail implementation (including true and complementary versions of the domino stage) is used.
For example, referring to FIG. 1, a prior art domino logic gate circuit 10 provides signals OUT and OUT* on conductors 14 and 16 as a function of an input signal A1 . . . An, where OUT and OUT* both have a logic low state during a precharge phase and are complementary during an evaluate phase. OUT and OUT* may be inputs to a next domino stage. Circuit 10 includes a domino stage 18 and a domino stage 20 and static stages 24 and 26. In the particular prior art embodiment illustrated, static stages 24 and 26 are inverters. In this disclosure, signals on conductors 28 and 30 are called domino stage intermediate signals (or INT). There are referred to as intermediate because they are not ready for the next domino stage because they have a logic high state rather than a logic low state in the precharge phase. Inverters 24 and 26 provide signals OUT and OUT* are conductors 14 and 16, respectively. In the example of circuit 10, the function of domino stage 18 is a NOR function, the result of which is inverted by inverter 24 to produce an OR function (i.e., where OUT is the logical OR of inputs A1 . . . An). The function of domino stage 20 is an OR function, the result of which is inverter by inverter 26 to produce a NOR function (i.e., OUT* is the complement of the logical OR of inputs A1 . . . An).
A disadvantage of circuit 10 is that it requires both a domino stage and a complementary domino stage, leading to approximately twice the area and power consumption.
Another disadvantage of circuit 10 is that complementary domino stage 20 includes stacked transistors which can cause significant delay in switching states.